1. Field of the Invention
The present invention generally relates to exchanging packets of data on an interconnect bus connecting two devices, and more particularly, to measuring and verifying the performance of such an exchange.
2. Description of the Related Art
A system on a chip (SOC) generally includes one or more integrated processor cores, some type of embedded memory such as a cache shared between the processor cores, and peripheral interfaces such as an external bus interface, on a single chip to form a complete (or nearly complete) system. The external bus interface is often used to pass data in packets over an external bus between these systems and an external device such as an external memory controller, Input/Output (I/O) controller, or graphics processing unit (GPU).
The performance of such a system may depend on several factors which may include device characteristics, characteristics of interconnect buses, memory hierarchy, operating system, and various other factors. A reasonable prediction of ranges for system performance can still be made after considering such factors. However, it is generally desirable to verify that performance falls within these ranges during simulation. For example, it may be desirable to verify that the throughput (or bandwidth) and the latency (or response time) of communication over an interconnect bus between a transmitting and receiving device fall within their predicted range.
Conventionally, simulation involves running predefined test cases modeled to emulate normal system operation. During simulation, bus traffic is monitored, interesting events on the bus are captured, and performance is measured based on the captured events. The captured events and their performance metrics are recorded in a simulation log. It is only after simulation that a user can view all the bus events in the simulation log and identify categories of events that fall outside the predicted performance range. However, because the information contained in the simulation logs is rather cryptic, significant effort will be required to manually analyze, identify and parse those categories of events that do not fall within their performance range. Another problem with conventional simulation is that predefined test cases may not adequately test a given category of bus events. For example, a test case may not contain a sufficient number of read operations. As a result, the performance measurements for the read operation may not be statistically significant.
Yet another problem with the conventional testing method is that degradations in performance are unlikely to be detected, without tedious manual analysis, when the predicted range of performance is too lenient. For example, if the average latency associated with a particular transaction between two devices is predicted to be 1 second, but the measured average latency is only 0.2 seconds, then a degradation of the average latency from 0.2 seconds to 0.8 seconds is unlikely to be caught even though there is a significant, undesired change in performance.
Accordingly, what is needed is improved methods and apparatus for measuring and verifying performance of packet based data exchanges between devices connected by an interconnect bus.